AXI4 Implementations in FPGA Designs
Learn AXI4 Bus implementation for your next FPGA design in Intel/Altera or AMD/Xilinx
4.69 (68 reviews)
651
students
8 hours
content
Jan 2025
last update
$74.99
regular price
What you will learn
Learn the FPGA based AXI4 Bus Protocol, including AXI4-Lite and AXI4 Stream with RTL / Verification in VHDL and Verilog
AXI4 Bus signals and Master / Slave Handshaking
Verification of the AXI4 Protocol and interfacing to Vendor IP
Simulation Demonstrations in Verilog and VHDL with sample code files
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5807956
udemy ID
2/6/2024
course created date
2/17/2024
course indexed date
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