Digital Timing Basics for VLSI Interview & SoC Design

A VLSI Course on Timing Concepts frequently used in Physical Design (Static Timing Analysis - STA), RTL & Circuit Design
4.45 (609 reviews)
Udemy
platform
English
language
Hardware
category
Learnin28days Academy
instructor
Digital Timing Basics for VLSI Interview & SoC Design
3,370
students
4 hours
content
Dec 2022
last update
$24.99
regular price

What you will learn

Basics of Flop & Latch Timings

Set-up, Hold, Clock to Q, Clock Skew

Set-up & Hold violation checks

Set-up & Hold violation fixes

Latency Minimization

Set-up & Hold Margin in Digital Ckts

Min & Max Path Analysis

Clock Gating

F-V Curve in SoC

Screenshots

Digital Timing Basics for VLSI Interview & SoC Design - Screenshot_01Digital Timing Basics for VLSI Interview & SoC Design - Screenshot_02Digital Timing Basics for VLSI Interview & SoC Design - Screenshot_03Digital Timing Basics for VLSI Interview & SoC Design - Screenshot_04
Related Topics
4204254
udemy ID
7/25/2021
course created date
8/16/2021
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