VSD - Functional Verification Using Embedded-UVM - Part 1

Introduction to Discrete Event Simulation Technology, Functional Verification, Getting acquainted with Simulation tools
4.04 (14 reviews)
Udemy
platform
English
language
Hardware
category
Kunal Ghosh
instructor
VSD - Functional Verification Using Embedded-UVM - Part 1
186
students
3 hours
content
Nov 2019
last update
$39.99
regular price

What you will learn

SoC design flow, role of Functional Verification

Logic Modeling, Introduction to Verilog

Concept of Hierarchy, Simulation-Time, and Concurrency in Hardware Modeling

Simulation Technology, Discrete Event Simulation

Verification Trends and Challenges

Concepts and Principles of Functional Verification

Testbench Architecture and Components

Lab – Tool Setup and Usage -- a simple DUT with traditional Verilog testbench will be provided with a Makefile to compile and simulate – Debug using waveforms

Screenshots

VSD - Functional Verification Using Embedded-UVM - Part 1 - Screenshot_01VSD - Functional Verification Using Embedded-UVM - Part 1 - Screenshot_02VSD - Functional Verification Using Embedded-UVM - Part 1 - Screenshot_03VSD - Functional Verification Using Embedded-UVM - Part 1 - Screenshot_04
Related Topics
2636384
udemy ID
11/2/2019
course created date
11/6/2019
course indexed date
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VSD - Functional Verification Using Embedded-UVM - Part 1 - Coupon | Comidoc