Hands-On ZYNQ: Mastering AXI4 Bus Protocol
Create Verilog and C codes for implementing the AXI4 bus protocol on ZYNQ FPGA
4.23 (165 reviews)
1,429
students
3.5 hours
content
Feb 2025
last update
$44.99
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What you will learn
Use Xilinx AXI4-based IP Cores
Create your own AXI4-based IP Cores from scratch
Create an AXI4-based Hardware Accelerator IP Core (GCD case study)
Create an AXI4-based Transceiver IP Core (UART case study)
1569552
udemy ID
2/25/2018
course created date
2/15/2021
course indexed date
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