SOC Verification using SystemVerilog

A comprehensive course that teaches System on Chip design verification concepts and coding in SystemVerilog Language
4.30 (6262 reviews)
Udemy
platform
English
language
Hardware
category
Ramdas Mozhikunnath M
instructor
SOC Verification using SystemVerilog
56,075
students
4.5 hours
content
May 2016
last update
FREE
regular price

What you will learn

Learn the important concepts in SOC/ASIC/VLSI design verification flow

Learn the System Verilog language for Functional Verification usage

Be ready and qualified for a Verification job in semiconductor industry

Udemy Certification on successful course completion

Be able to code, simulate and verify SystemVerilog Testbenches

Screenshots

SOC Verification using SystemVerilog - Screenshot_01SOC Verification using SystemVerilog - Screenshot_02SOC Verification using SystemVerilog - Screenshot_03SOC Verification using SystemVerilog - Screenshot_04
Related Topics
156022
udemy ID
1/31/2014
course created date
7/28/2019
course indexed date
Bot
course submited by
SOC Verification using SystemVerilog - Free course | Comidoc