Verilog HDL Fundamentals for Digital Design and Verification
Build a strong Verilog language foundation by implementing combinational / sequential digital circuits and testbenches
4.49 (1193 reviews)
6,702
students
5.5 hours
content
Jun 2024
last update
$79.99
regular price
What you will learn
Master the basics of Verilog language for designing synthesizable digital circuits for ASIC / FPGA
Differentiate between Verilog structural / dataflow / behavioral design styles and how / when to use them in Digital Design and Verification
Implement combinational and sequential digital circuits using Verilog HDL starting from schematics or functional specifications
Create and simulate a Verilog testbench for a digital circuit starting from its functional specifications
Examine the behavior of a digital circuit receiving stimulus in a testbench, using an industry-level simulator (free for academic purposes)
Explicit visual explanations for the 80+ downloadable code examples, circuits, and testbenches offering you increased retention and accelerated learning
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udemy ID
8/24/2021
course created date
9/27/2021
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