Vivado Basics: Learn FPGA Design with a PCIe Project
Master FPGA Development with Vivado: Design Xilinx FPGAs from Scratch Using VHDL or Verilog
3.77 (149 reviews)
13,700
students
8 hours
content
Nov 2024
last update
$44.99
regular price
What you will learn
Master the Vivado Design Suite: Learn how to install, navigate, and use Vivado for FPGA design, simulation, and debugging.
Design FPGA Projects from Scratch: Understand how to create and implement projects using Xilinx FPGAs, including block design and adding IP cores.
Simulate and Debug Designs: Gain hands-on experience simulating projects with Vivado and ModelSim, and debug them using tools like the Integrated Logic Analyzer
Develop Advanced Features: Learn to work with PCIe communication, AXI interfaces, and Zynq 7000 processors for real-world applications.
How to create Bit or Mcs file, and even uploading it to a development board!
How to open SDK project.
Axi-Bus, Streamed and Memory-mapped IP's and differences.
How to setup the PCIe root complex write a full communication to the Pcie end point and how to simulate the PCIe.
Adding ILA ,integrated logic analyzer, the strongest tool for real-time debug.
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2587268
udemy ID
10/2/2019
course created date
11/24/2020
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