VSD - Mixed-signal RISC-V based SoC on FPGA

FPGA flow for Mixed Signal SoC with RISC-V based core and PLL IP
3.88 (8 reviews)
Udemy
platform
English
language
Design Tools
category
Kunal Ghosh
instructor
VSD - Mixed-signal RISC-V based SoC on FPGA
113
students
1.5 hours
content
Jul 2021
last update
$39.99
regular price

What you will learn

FPGA flow vs ASIC flow

Basic mixed-signal RISC-V based SoC RTL design and simulations

FPGA Synthesis, bit-stream generation and simulation

Screenshots

VSD - Mixed-signal RISC-V based SoC on FPGA - Screenshot_01VSD - Mixed-signal RISC-V based SoC on FPGA - Screenshot_02VSD - Mixed-signal RISC-V based SoC on FPGA - Screenshot_03VSD - Mixed-signal RISC-V based SoC on FPGA - Screenshot_04
Related Topics
4185794
udemy ID
7/15/2021
course created date
7/18/2021
course indexed date
Bot
course submited by